The present invention relates: to a semiconductor device and a manufacturing method thereof; and more specifically to a semiconductor device including an n-channel transistor and a p-channel transistor having an insulation film of a high electric permittivity and a manufacturing method of the semiconductor device.
A CMIS (Complementary Metal Insulator Semiconductor) transistor having an n-channel MIS (Metal Insulator Semiconductor) transistor and a p-channel MIS transistor is widely used. In a CMIS transistor, a plurality of so-called dummy patterns that are different from legitimate transistors are arranged at the peripheries of the legitimate (functional) n-channel and p-channel transistors functioning as transistors. A dummy pattern is formed with the aim of improving the flatness of an uppermost plane at a treatment called CMP (Chemical Mechanical Polishing) to flatten the uppermost plane such as an interlayer insulation film formed in the manufacturing step of a semiconductor integrated circuit. A semiconductor integrated circuit device having a plurality of dummy patterns at the peripheries of legitimate functional circuits is disclosed in Japanese Unexamined Patent Publication No. 2007-250705 (hereunder referred to as “Patent Literature 1”) for example.